The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 23, 2010
Filed:
Aug. 18, 2006
Wen-han Hung, Kaohsiung, TW;
Cheng-tung Huang, Kaohsiung, TW;
Li-shian Jeng, Taitung, TW;
Kun-hsien Lee, Tainan, TW;
Shyh-fann Ting, Kaohsiung County, TW;
Tzyy-ming Cheng, Hsinchu, TW;
Chia-wen Liang, Hsinchu, TW;
Wen-Han Hung, Kaohsiung, TW;
Cheng-Tung Huang, Kaohsiung, TW;
Li-Shian Jeng, Taitung, TW;
Kun-Hsien Lee, Tainan, TW;
Shyh-Fann Ting, Kaohsiung County, TW;
Tzyy-Ming Cheng, Hsinchu, TW;
Chia-Wen Liang, Hsinchu, TW;
United Microelectronics Corp., Hsinchu, TW;
Abstract
A method of fabricating a semiconductor device is provided. A substrate is first provided, and then several IO devices and several core devices are formed on the substrate, wherein those IO devices include IO PMOS and IO NMOS, and those core devices include core PMOS and core NMOS. Thereafter, a buffer layer is formed on the substrate, and then the buffer layer except a surface of the IO PMOS is removed in order to reduce the negative bias temperature instability (NBTI) of the IO PMOS. Afterwards, a tensile contact etching stop layer (CESL) is formed on the IO NMOS and the core NMOS, and a compressive CESL is formed the core PMOS.