The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 16, 2010
Filed:
Nov. 07, 2006
Pei-haw Tsao, Tai-Chung, TW;
Liang-chen Lin, Baoshan Shiang, TW;
Pao-kang Niu, Hsinchu, TW;
I-tai Liu, Yung-Ho, TW;
Bill Kiang, Hsinchu, TW;
Pei-Haw Tsao, Tai-Chung, TW;
Liang-Chen Lin, Baoshan Shiang, TW;
Pao-Kang Niu, Hsinchu, TW;
I-Tai Liu, Yung-Ho, TW;
Bill Kiang, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Abstract
An improved via arrangement for a bonding pad structure is disclosed comprising an array of vias surrounded by a line via. The line via provides a barrier to cracks in the dielectric layer encompassing the via array. Although cracks are able to spread relatively unhindered between the vias of the via array, they are blocked by the line via and thus can not spread to neighboring regions of the chip or wafer. The line via can be provided in a variety of shapes and dimensions, to suit a desired application. Additionally, due to its substantially uninterrupted length, the line via provides added strength to the bond pad.