The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 16, 2010
Filed:
Nov. 13, 2006
Guoqing Yu, SuZhou Industrial Park, CN;
Youjun Wang, SuZhou Industrial Park, CN;
Qinqin Xu, SuZhou Industrial Park, CN;
Qingwei Wang, SuZhou Industrial Park, CN;
Wei Wang, SuZhou Industrial Park, CN;
Guoqing Yu, SuZhou Industrial Park, CN;
Youjun Wang, SuZhou Industrial Park, CN;
Qinqin Xu, SuZhou Industrial Park, CN;
Qingwei Wang, SuZhou Industrial Park, CN;
Wei Wang, SuZhou Industrial Park, CN;
China Wafer Level CSP Ltd., Suzhou Industrial Park, CN;
Abstract
The present invention disclosed a wafer level chip size packaged chip device with a double-layer lead structure and methods of fabricating the same. The double-layer lead is designed to meet a tendency of increasing quantity per area of peripheral arrayed compatible pads on a semiconductor chip, and also to save more space for layout of lead on the chip bottom surface for avoiding potential short inbetween which happen in increasing probability with increasing quantity per area on the condition of one-layer lead.