The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 05, 2010
Filed:
Nov. 06, 2008
Kun-hsien Lee, Tai-Nan, TW;
Cheng-tung Huang, Kao-Hsiung, TW;
Wen-han Hung, Kao-Hsiung, TW;
Shyh-fann Ting, Tai-Nan, TW;
Li-shian Jeng, Tai-Tung Hsien, TW;
Tzyy-ming Cheng, Hsin-Chu, TW;
Neng-kuo Chen, Hsin-Chu, TW;
Shao-ta Hsu, Tai-Nan, TW;
Teng-chun Tsai, Hsin-Chu, TW;
Chien-chung Huang, Tai-Chung Hsien, TW;
Kun-Hsien Lee, Tai-Nan, TW;
Cheng-Tung Huang, Kao-Hsiung, TW;
Wen-Han Hung, Kao-Hsiung, TW;
Shyh-Fann Ting, Tai-Nan, TW;
Li-Shian Jeng, Tai-Tung Hsien, TW;
Tzyy-Ming Cheng, Hsin-Chu, TW;
Neng-Kuo Chen, Hsin-Chu, TW;
Shao-Ta Hsu, Tai-Nan, TW;
Teng-Chun Tsai, Hsin-Chu, TW;
Chien-Chung Huang, Tai-Chung Hsien, TW;
United Microelectronics Corp., Hsin-Chu, TW;
Abstract
A method of manufacturing a MOS transistor device is provided. First, a semiconductor substrate having a gate structure is prepared. The gate structure has two sidewalls and a liner on the sidewalls. Subsequently, a stressed cap layer is formed on the semiconductor substrate, and covers the gate structure and the liner. Next, an activating process is performed. Furthermore, the stressed cap layer is etched to be a salicide block. Afterward, a salicide process is performed to form a silicide layer on the regions that are not covered by the stressed cap layer.