The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 24, 2009
Filed:
Jul. 17, 2007
Chia-wen Liang, Hsin-Chu, TW;
Cheng-tung Huang, Kao-Hsiung, TW;
Shyh-fann Ting, Tai-Nan, TW;
Chih-chiang Wu, Taichung County, TW;
Shih-chieh Hsu, Hsinchu, TW;
Li-shian Jeng, Tai-Tung Hsien, TW;
Kun-hsien Lee, Tai-Nan, TW;
Meng-yi Wu, Kaohsiung County, TW;
Wen-han Hung, Kao-Hsiung, TW;
Tzyy-ming Cheng, Hsin-Chu, TW;
Chia-Wen Liang, Hsin-Chu, TW;
Cheng-Tung Huang, Kao-Hsiung, TW;
Shyh-Fann Ting, Tai-Nan, TW;
Chih-Chiang Wu, Taichung County, TW;
Shih-Chieh Hsu, Hsinchu, TW;
Li-Shian Jeng, Tai-Tung Hsien, TW;
Kun-Hsien Lee, Tai-Nan, TW;
Meng-Yi Wu, Kaohsiung County, TW;
Wen-Han Hung, Kao-Hsiung, TW;
Tzyy-Ming Cheng, Hsin-Chu, TW;
United Microelectronics Corp., Hsin-Chu, TW;
Abstract
A method for manufacturing CMOS transistors includes an etching back process alternatively performed after the gate structure formation, the lightly doped drain formation, source/drain implantation, or SEG process to etch a hard mask layer covering and protecting a first type gate structure, and to reduce thickness deviation between the hard masks covering the first type gate structure and a second type gate structure. Therefore the damage to spacers, STIs, and the profile of the gate structures due to the thickness deviation is prevented.