The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2009

Filed:

Jul. 19, 2006
Applicants:

Kun-hsien Lee, Tainan, TW;

Cheng-tung Huang, Kaohsiung, TW;

Li-shian Jeng, Taitung, TW;

Wen-han Hung, Kaohsiung, TW;

Shyh-fann Ting, Gangshan Township, Kaohsiung County, TW;

Jing-yi Huang, Kaohsiung, TW;

Tzyy-ming Cheng, Hsinchu, TW;

Chia-wen Liang, Hsinchu, TW;

Inventors:

Kun-Hsien Lee, Tainan, TW;

Cheng-Tung Huang, Kaohsiung, TW;

Li-Shian Jeng, Taitung, TW;

Wen-Han Hung, Kaohsiung, TW;

Shyh-Fann Ting, Gangshan Township, Kaohsiung County, TW;

Jing-Yi Huang, Kaohsiung, TW;

Tzyy-Ming Cheng, Hsinchu, TW;

Chia-Wen Liang, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 21/8234 (2006.01); H01L 21/3205 (2006.01); H01L 21/4763 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of fabricating a metal-oxide-semiconductor transistor is provided. A first gate structure and a second gate structure are formed on a substrate. The first gate structure has a dimension greater than the second gate structure. Then, first lightly doped drain regions are formed in the substrate on two sides of the first gate structure. A lightly doped drain annealing process is performed. Next, second lightly doped drain regions are formed in the substrate on two sides of the second gate structure. First spacers are formed on the sidewalls of the first gate structure and second spacers are formed on the sidewalls of the second gate structure at the same time. Afterwards, first source/drain regions are formed in the substrate on two sides of the first spacers and second source/drain regions are formed in the substrate on two sides of the second spacers. A source/drain annealing process is performed.


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