The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 01, 2009
Filed:
Oct. 05, 2007
Ho-ming Tong, Taipei, TW;
Teck-chong Lee, Kaohsiung, TW;
Chao-fu Weng, Tainan, TW;
Chian-chi Lin, Tainan, TW;
Chih-nan Wei, Kaohsiung, TW;
Song-fu Yang, Kaohsiung, TW;
Chia-jung Tsai, Tainan, TW;
Kao-ming Su, Kaohsiung, TW;
Ho-Ming Tong, Taipei, TW;
Teck-Chong Lee, Kaohsiung, TW;
Chao-Fu Weng, Tainan, TW;
Chian-Chi Lin, Tainan, TW;
Chih-Nan Wei, Kaohsiung, TW;
Song-Fu Yang, Kaohsiung, TW;
Chia-Jung Tsai, Tainan, TW;
Kao-Ming Su, Kaohsiung, TW;
Advanced Semiconductor Engineering, Inc., Kaohsiung, TW;
Abstract
A wire-bonding method for a wire-bonding apparatus is provided. The wire-bonding apparatus includes at least a first wire-bonder and a second wire-bonder for respectively bonding at least several first chips in a first region and several second chips in a second region on a substrate simultaneously. The wire-bonding method includes following steps. First, initial position coordinates of the first region and the second region are obtained. Next, it is determined whether a space between the first region and the second region is greater than a predetermined space. When the space between the first region and the second region is greater than the predetermined space, the first wire-bonder and the second wire-bonder respectively bond the first chips and the second chips simultaneously.