The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 25, 2009
Filed:
Jun. 11, 2002
Yong Poo Chia, Singapore, SG;
Suan Jeung Boon, Singapore, SG;
Siu Waf Low, Singapore, SG;
Yong Loo Neo, Singapore, SG;
Bok Leng Ser, Singapore, SG;
Yong Poo Chia, Singapore, SG;
Suan Jeung Boon, Singapore, SG;
Siu Waf Low, Singapore, SG;
Yong Loo Neo, Singapore, SG;
Bok Leng Ser, Singapore, SG;
Micron Technology, Inc., Boise, ID (US);
Abstract
A wafer level package, and a semiconductor wafer, electronic system, and a memory module that include one or more of the wafer level packages, and methods of fabricating the die packages on a wafer level, and integrated circuit modules that include one or more packages are provided. In one embodiment, the die package comprises a redistribution layer interconnecting two or more dies disposed on a substrate, typically a semiconductor wafer, the redistribution layer including a first trace connecting a bond pad of each of two dies, and a second trace connecting one of the bond pads of the two dies to a ball pad. The die package of the invention can comprise memory devices such as static random access memories (SRAMs), and can be incorporated into a variety of electronic systems as part of a memory package such as single in line memory modules (SIMMs) or dual in line memory modules.