The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 2009

Filed:

Mar. 22, 2005
Applicants:

Sairam Agraharam, Phoenix, AZ (US);

Carlton Hanna, Chandler, AZ (US);

Dongming He, Gilbert, AZ (US);

Vasudeva Atluri, Scottsdale, AZ (US);

Debendra Mallik, Chandler, AZ (US);

Matthew Escobido, Quezon, PH;

Sujit Sharan, Gilbert, AZ (US);

Inventors:

Sairam Agraharam, Phoenix, AZ (US);

Carlton Hanna, Chandler, AZ (US);

Dongming He, Gilbert, AZ (US);

Vasudeva Atluri, Scottsdale, AZ (US);

Debendra Mallik, Chandler, AZ (US);

Matthew Escobido, Quezon, PH;

Sujit Sharan, Gilbert, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
Abstract

In one embodiment, the invention provides a method comprising fabricating a die bump on a die, the die bump being shaped and dimensioned to at least reduce the flow of solder material used, to attach the die bump to a package substrate, towards an under bump metallurgy (UBM) layer located below the die bump. Advantageously, the method may comprise performing a substrate reflow operation to attach the package substrate to the die bump, without performing a separate wafer reflow operation to reflow the die bump.


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