The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 03, 2009
Filed:
Nov. 17, 2003
Dennis Ciplickas, San Jose, CA (US);
Joe Davis, Unterschleissheim, DE;
Christopher Hess, San Ramon, CA (US);
Sherry Lee, San Jose, CA (US);
Enrico Malavasi, Mountain View, CA (US);
Abdulmobeen Mohammad, Sunnyvale, CA (US);
Ratibor Radojcic, San Diego, CA (US);
Brian Stine, Los Altos Hills, CA (US);
Rakesh Vallishayee, San Jose, CA (US);
Stefano Zanella, San Jose, CA (US);
Nicola Dragone, Vobarno, IT;
Carlo Guardiani, Verona, IT;
Michel Quarantelli, Noceto, IT;
Stefano Tonello, Breganze, IT;
Joshi Aniruddha, Irvine, CA (US);
Dennis Ciplickas, San Jose, CA (US);
Joe Davis, Unterschleissheim, DE;
Christopher Hess, San Ramon, CA (US);
Sherry Lee, San Jose, CA (US);
Enrico Malavasi, Mountain View, CA (US);
Abdulmobeen Mohammad, Sunnyvale, CA (US);
Ratibor Radojcic, San Diego, CA (US);
Brian Stine, Los Altos Hills, CA (US);
Rakesh Vallishayee, San Jose, CA (US);
Stefano Zanella, San Jose, CA (US);
Nicola Dragone, Vobarno, IT;
Carlo Guardiani, Verona, IT;
Michel Quarantelli, Noceto, IT;
Stefano Tonello, Breganze, IT;
Joshi Aniruddha, Irvine, CA (US);
PDF Solutions, Inc., San Jose, CA (US);
Abstract
An integrated circuit is designed to improve yield when manufacturing the integrated circuit, by obtaining a design element from a set of design elements used in designing integrated circuits. A variant design element is created based on the obtained design element, where a feature of the obtained design element is modified to create the variant design element. A yield to area ratio for the variant design element is determined. If the yield to area ratio of the variant design element is greater than a yield to area ratio of the obtained design element, the variant design element is retained to be used in designing the integrated circuit.