The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 03, 2009
Filed:
Apr. 07, 2006
Kun-hsien Lee, Tainan, TW;
Cheng-tung Huang, Kaohsiung, TW;
Wen-han Hung, Kaohsiung, TW;
Shyh-fann Ting, Kaohsiung County, TW;
Li-shian Jeng, Taitung, TW;
Tzyy-ming Cheng, Hsinchu, TW;
Chia-wen Liang, Hsinchu, TW;
Kun-Hsien Lee, Tainan, TW;
Cheng-Tung Huang, Kaohsiung, TW;
Wen-Han Hung, Kaohsiung, TW;
Shyh-Fann Ting, Kaohsiung County, TW;
Li-Shian Jeng, Taitung, TW;
Tzyy-Ming Cheng, Hsinchu, TW;
Chia-Wen Liang, Hsinchu, TW;
United Microelectronics Corp., Hsinchu, TW;
Abstract
A method for fabricating a semiconductor device is provided. First, a substrate is provided, and a first-type MOS (metallic oxide semiconductor) transistor, an input/output (I/O) second-type MOS transistor, and a core second-type MOS transistor are formed on the substrate. Then, a first stress layer is formed to overlay the substrate, the first-type MOS transistor, the I/O second-type MOS transistor, and the core second-type MOS transistor. Then, at least the first stress layer on the core second-type MOS transistor is removed to reserve at least the first stress layer on the first-type MOS transistor. Finally, a second stress layer is formed on the core second-type MOS transistor.