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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7446398 B1

PDFFull Text
Date of Patent:
Nov. 04, 2008

Filed:

Aug. 01, 2006

Bump pattern design for flip chip semiconductor package

Applicants:

Pao-kang Niu, Hsinchu, TW;

Pei-haw Tsao, Tai-chung, TW;

Hao-yi Tsai, Hsinchu, TW;

Yung-kuan Hsiao, Chu-bei, TW;

Chung Yu Wang, Hsin Chu, TW;

Shang-yun Hou, Jubei, TW;

Lin Yu-ting, Hsin-Chu, TW;

Inventors:

Pao-Kang Niu, Hsinchu, TW;

Pei-Haw Tsao, Tai-chung, TW;

Hao-Yi Tsai, Hsinchu, TW;

Yung-Kuan Hsiao, Chu-bei, TW;

Chung Yu Wang, Hsin Chu, TW;

Shang-Yun Hou, Jubei, TW;

Lin Yu-Ting, Hsin-Chu, TW;

Assignee:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Attorney:

Duane Morris LLP

Primary Examiner:

Alexander O Williams

Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/488 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
Abstract

A bump pattern design for flip chip semiconductor packages includes a pattern of contact pads formed on a package substrate. Each contact pad is adapted to receive a corresponding solder bump from a semiconductor chip attached thereto. The pattern includes a central portion and a peripheral portion with a transition portion therebetween. The transition portion has a lower pattern density than the central portion and peripheral portions. In the peripheral portion is at least one outer portion having a pattern density less than the average pattern density of the central portion. The outer portions of reduced pattern density may be the corner sections in a rectangular bump pattern and may further include channels that are void of contact pads. The peripheral portion may include an average pitch between most of the rows and columns, but also an increased pitch between some adjacent rows and columns.

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Niu, Pao-Kang. (2008). Bump pattern design for flip chip semiconductor package (U.S. Patent No. 7446398). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7446398

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