Hsinchu, Taiwan

Lin Yu-Ting

This inventor holds 1 USPTO granted patent. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2008.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Lin Yu-Ting. Retrieved from https://idiyas.com/inventor/lin-yu-ting

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0

Average Co-Inventor Count = 7.0

ph-index = 1

Forward Citations = 7(Granted Patents)


Company Filing History:


Years Active: 2008

Loading Chart...
1 patent (USPTO):Explore Patents

Title: Lin Yu-Ting: Semiconductor Packaging Inventor

Introduction

Lin Yu-Ting is an inventor associated with Hsinchu, Taiwan, and Taiwan Semiconductor Manufacturing Company Limited. His patent work addresses bump-pattern design for flip-chip semiconductor packages.

Latest Patents

The provided information lists one patent for Lin Yu-Ting: “Bump Pattern Design for Flip Chip Semiconductor Package.” The invention describes contact pads arranged on a package substrate to receive solder bumps from an attached semiconductor chip. Its layout uses central, transition, and peripheral portions, with the transition portion having a lower pattern density than the central and peripheral portions. Reduced-density outer areas, including corner sections and channels without contact pads, can help manage the pattern, while selected rows and columns may have increased spacing.

Career Highlights

Lin Yu-Ting’s listed patent reflects work on the arrangement and spacing of contacts in flip-chip semiconductor packaging. The design focuses on varying pattern density and pitch across different regions of a package substrate.

Collaborations

The provided information names Shang-Yun Hou and Hao-Yi Tsai as Lin Yu-Ting’s coworkers. It does not specify their roles in the patent or whether they collaborated on the invention.

Conclusion

Lin Yu-Ting’s recorded patent concerns a differentiated bump-pattern layout for flip-chip semiconductor packages, highlighting his contribution to semiconductor packaging design.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…