The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 15, 2008
Filed:
Nov. 29, 2005
Yi-ming Sheu, Hsinchu, TW;
Da-wen Lin, Taipin, TW;
Cheng-ku Chen, Hsinchu, TW;
Po-ying Yeh, Tainan, TW;
Shi-shung Peng, Hsinchu County, TW;
Chung-cheng Wu, Hsin-Chu, TW;
Yi-Ming Sheu, Hsinchu, TW;
Da-Wen Lin, Taipin, TW;
Cheng-Ku Chen, Hsinchu, TW;
Po-Ying Yeh, Tainan, TW;
Shi-Shung Peng, Hsinchu County, TW;
Chung-Cheng Wu, Hsin-Chu, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Abstract
A method to reduce the inverse narrow width effect in NMOS transistors is described. An oxide liner is deposited in a shallow trench that is formed to isolate active areas in a substrate. A photoresist plug is formed in the shallow trench and is recessed below the top of the substrate to expose the top portion of the oxide liner. An angled indium implant through the oxide liner into the substrate is then performed. The plug is removed and an insulator is deposited to fill the trenches. After planarization and wet etch steps, formation of a gate dielectric layer and a patterned gate layer, the NMOS transistor exhibits an improved Vt roll-off of 40 to 45 mVolts for both long and short channels. The improvement is achieved with no degradation in junction or isolation performance. The indium implant dose and angle may be varied to provide flexibility to the process.