The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 01, 2008
Filed:
Nov. 13, 2006
Guoqing Yu, SuZhou Industrial Park, CN;
Youjun Wang, SuZhou Industrial Park, CN;
Qinqin Xu, SuZhou Industrial Park, CN;
Qingwei Wang, SuZhou Industrial Park, CN;
Wei Wang, SuZhou Industrial Park, CN;
Guoqing Yu, SuZhou Industrial Park, CN;
Youjun Wang, SuZhou Industrial Park, CN;
Qinqin Xu, SuZhou Industrial Park, CN;
Qingwei Wang, SuZhou Industrial Park, CN;
Wei Wang, SuZhou Industrial Park, CN;
China Wafer Level CSP Ltd., SuZhou Industrial Park, CN;
Abstract
The present invention provide a wafer level chip size packaged chip device with a N-shape junction at which external leads electrically connect to peripheral arrayed compatible pads and a method of fabricating the same. In the wafer level chip size package, with such an n-shape junction instead of a conventional T-shape junction observed in Shellcase type wafer level chip size package technology, electrical connections between compatible pads and external leads are more reliable due to larger connection area than the counterpart in the T-shape junction.