The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 01, 2008
Filed:
Apr. 19, 2007
Hiroji Hanawa, Sunnyvale, CA (US);
Kartik Ramaswamy, Santa Clara, CA (US);
Kenneth S. Collins, San Jose, CA (US);
Amir Al-bayati, San Jose, CA (US);
Biagio Gallo, Los Gatos, CA (US);
Andrew Nguyen, San Jose, CA (US);
Hiroji Hanawa, Sunnyvale, CA (US);
Kartik Ramaswamy, Santa Clara, CA (US);
Kenneth S. Collins, San Jose, CA (US);
Amir Al-Bayati, San Jose, CA (US);
Biagio Gallo, Los Gatos, CA (US);
Andrew Nguyen, San Jose, CA (US);
Applied Materials, Inc., Santa Clara, CA (US);
Abstract
Device-enhancing coatings are deposited on CMOS devices by successively masking with photoresist each one of the sets of N-channel and P-channel devices while unmasking or leaving unmasked the other set, and after each step of successively masking one of the sets of devices, carrying out low temperature CVD steps with a toroidal RF plasma current while applying an RF plasma bias voltage. The temperature of the workpiece is held below a threshold photoresist removal temperature. The RF bias voltage is held at a level at which the coating is deposited with a first stress when the unmasked set consists of the P-channel devices and with a second stress when the unmasked set consists of N-channel devices.