The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 03, 2008

Filed:

Dec. 07, 2004
Applicants:

Justin K. Brask, Portland, OR (US);

Sangwoo Pae, Beaverton, OR (US);

Jack Kavalieros, Portland, OR (US);

Matthew V. Metz, Hillsboro, OR (US);

Mark L. Doczy, Beaverton, OR (US);

Suman Datta, Beaverton, OR (US);

Robert S. Chau, Beaverton, OR (US);

Jose A. Maiz, Portland, OR (US);

Inventors:

Justin K. Brask, Portland, OR (US);

Sangwoo Pae, Beaverton, OR (US);

Jack Kavalieros, Portland, OR (US);

Matthew V. Metz, Hillsboro, OR (US);

Mark L. Doczy, Beaverton, OR (US);

Suman Datta, Beaverton, OR (US);

Robert S. Chau, Beaverton, OR (US);

Jose A. Maiz, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for making a semiconductor device is described. That method comprises adding nitrogen to a silicon dioxide layer to form a nitrided silicon dioxide layer on a substrate. After forming a sacrificial layer on the nitrided silicon dioxide layer, the sacrificial layer is removed to generate a trench. A high-k gate dielectric layer is formed on the nitrided silicon dioxide layer within the trench, and a metal gate electrode is formed on the high-k gate dielectric layer.


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