The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7366575 B1

PDF
Full Text
Expired
Date of Patent:
Apr. 29, 2008

Filed:

Dec. 30, 2005
Applicants:

Matthew A. Ring, Aloha, OR (US);

Scot Goerutiz, Phoenix, AZ (US);

Kimberly A. Ryglelski, Gilbert, AZ (US);

Anju Narendra, Beaverton, OR (US);

Kevin E. Heldrich, Beaverton, OR (US);

Brook D. Ferney, Aloha, OR (US);

Inventors:

Matthew A. Ring, Aloha, OR (US);

Scot Goerutiz, Phoenix, AZ (US);

Kimberly A. Ryglelski, Gilbert, AZ (US);

Anju Narendra, Beaverton, OR (US);

Kevin E. Heldrich, Beaverton, OR (US);

Brook D. Ferney, Aloha, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G05B 13/02 (2006.01); G06F 19/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Methods of controlling polishing of wafers are disclosed. In one aspect, a method may include measuring one or more pre-polish thicknesses of one or more layers of a wafer. The one or more layers may then be polished. Then a post-polish thickness of a layer of the wafer may be measured. Polishing may be controlled by using feed-forward control with the one or more pre-polish thicknesses and by using feed-back control with the post-polish thickness. Machine-accessible software to perform such methods are also disclosed as are systems in which such methods may be implemented.


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