The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 25, 2007
Filed:
Dec. 27, 2002
Ebo Croffie, Portland, OR (US);
Colin Yates, Clackamas, OR (US);
Nicholas Eib, San Jose, CA (US);
Christopher Neville, Portland, OR (US);
Mario Garza, Sunnyvale, CA (US);
Neal Callan, Lake Oswego, OR (US);
Ebo Croffie, Portland, OR (US);
Colin Yates, Clackamas, OR (US);
Nicholas Eib, San Jose, CA (US);
Christopher Neville, Portland, OR (US);
Mario Garza, Sunnyvale, CA (US);
Neal Callan, Lake Oswego, OR (US);
LSI Corporation, Milpitas, CA (US);
Abstract
The invention provides a method of performing process window compliant corrections of a design layout. The invention includes an operator performing the following steps: (1) simulating Develop Inspect Critical Dimension (DI CD) at best exposure conditions using the provided original layout pattern; (2) simulating DI CD at predefined boundary exposure conditions using the provided original layout pattern; (3) if the DI CD from step (1) meets the target DI CD definition, and the DI CD from step (2) meets process window specifications, convergence takes place; and (4) modifying the layout pattern and repeating steps (2) through (3) until DI CD from step (2) reaches the specification limit if any portion of step (3) is not achieved.