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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7288822 B1

PDFFull Text
Date of Patent:
Oct. 30, 2007

Filed:

Apr. 07, 2006

Semiconductor structure and fabricating method thereof

Applicants:

Shyh-fann Ting, Gangshan Township, Kaohsiung County, TW;

Cheng-tung Huang, Kaohsiung, TW;

Wen-han Hung, Kaohsiung, TW;

Li-shian Jeng, Taitung, TW;

Kun-hsien Lee, Tainan, TW;

Tzyy-ming Cheng, Hsinchu, TW;

Jing-chang Wu, Douliou, TW;

Tzermin Shen, Hsinchu, TW;

Inventors:

Shyh-Fann Ting, Gangshan Township, Kaohsiung County, TW;

Cheng-Tung Huang, Kaohsiung, TW;

Wen-Han Hung, Kaohsiung, TW;

Li-Shian Jeng, Taitung, TW;

Kun-Hsien Lee, Tainan, TW;

Tzyy-Ming Cheng, Hsinchu, TW;

Jing-Chang Wu, Douliou, TW;

Tzermin Shen, Hsinchu, TW;

Assignee:

United Microelectronics Corp., Hsinchu, TW;

Attorney:

J.C. Patents

Primary Examiner:

Ida M Soward

Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 29/94 (2006.01); H01L 31/062 (2006.01); H01L 31/113 (2006.01); H01L 31/119 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor structure is disclosed, including a substrate having therein a first well of a first conductivity type and a second well of a second conductivity type, a first MOS transistor of the first conductivity type and a second MOS transistor of the second conductivity type. The first MOS transistor is disposed on the second well, including a gate structure on the second well and a strained layer of the first conductivity type in an opening in the second well beside the gate structure. The difference between the lattice parameter of a portion of the strained layer near the bottom of the opening and that of the substrate is less than the difference between the lattice parameter of a portion of the strained layer apart from the bottom of the opening and that of the substrate. The second MOS transistor is disposed on the first well.

Find Patent Forward Citations

Ting, Shyh-Fann. (2007). Semiconductor structure and fabricating method thereof (U.S. Patent No. 7288822). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7288822

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