The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 11, 2007
Filed:
Jan. 09, 2005
Zong-huei Lin, Tai-Chung, TW;
Hung-min Liu, Hsin-Chu, TW;
Jui-meng Jao, Miao- Li Hsien, TW;
Wen-tung Chang, Hsin-Chu, TW;
Kuo-ming Chen, Hsin-Chu Hsien, TW;
Kai-kuang Ho, Hsin-Chu, TW;
Zong-Huei Lin, Tai-Chung, TW;
Hung-Min Liu, Hsin-Chu, TW;
Jui-Meng Jao, Miao- Li Hsien, TW;
Wen-Tung Chang, Hsin-Chu, TW;
Kuo-Ming Chen, Hsin-Chu Hsien, TW;
Kai-Kuang Ho, Hsin-Chu, TW;
United Microelectronics Corp., Hsin-Chu, TW;
Abstract
A semiconductor wafer includes a plurality of active circuit die areas, each of which being bordered by a dicing line region through which the plurality of active circuit die areas are separated from each other by mechanical wafer dicing. Each of the plurality of active circuit die areas has four sides. An overcoat covers both the active circuit die areas and the dicing line region. An inter-layer dielectric layer is disposed underneath the overcoat. A reinforcement structure includes a plurality of holes formed within the dicing line region. The plurality of holes are formed by etching through the overcoat into the inter-layer dielectric layer and are disposed along the four sides of each active circuit die area. A die seal ring is disposed in between the active circuit chip area and the reinforcement structure.