The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 10, 2007
Filed:
Dec. 11, 2002
Method for depositing a metal layer on a semiconductor interconnect structure having a capping layer
Larry Clevenger, LaGrangeville, NY (US);
Timothy Joseph Dalton, Ridgefield, CT (US);
Mark Hoinkis, Fishkill, NY (US);
Steffen K. Kaldor, Fishkill, NY (US);
Kaushik Kumar, Beacon, NY (US);
Douglas C. LA Tulipe, Jr., Danbury, CT (US);
Soon-cheon Seo, White Plains, NY (US);
Andrew Herbert Simon, Fishkill, NY (US);
Yun-yu Wang, Poughquag, NY (US);
Chih-chao Yang, Beacon, NY (US);
Haining Yang, Wappingers Falls, NY (US);
Larry Clevenger, LaGrangeville, NY (US);
Timothy Joseph Dalton, Ridgefield, CT (US);
Mark Hoinkis, Fishkill, NY (US);
Steffen K. Kaldor, Fishkill, NY (US);
Kaushik Kumar, Beacon, NY (US);
Douglas C. La Tulipe, Jr., Danbury, CT (US);
Soon-Cheon Seo, White Plains, NY (US);
Andrew Herbert Simon, Fishkill, NY (US);
Yun-Yu Wang, Poughquag, NY (US);
Chih-Chao Yang, Beacon, NY (US);
Haining Yang, Wappingers Falls, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Infineon Technologies, AG, Munich, DE;
Abstract
Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor is covered by a capping layer and a dielectric layer. The dielectric layer is patterned so as to expose the capping layer. The capping layer is then sputter etched to remove the capping layer and expose the metal conductor. In the process of sputter etching, the capping layer is redeposited onto the sidewall of the pattern. Lastly, at least one layer is deposited into the pattern and covers the redeposited capping layer.