The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 05, 2007
Filed:
May. 19, 2003
Chia Yong Poo, Singapore, SG;
Boon Suan Jeung, Singapore, SG;
Chua Swee Kwang, Singapore, SG;
Low Siu Waf, Singapore, SG;
Chan Min Yu, Singapore, SG;
Neo Yong Loo, Singapore, SG;
Chia Yong Poo, Singapore, SG;
Boon Suan Jeung, Singapore, SG;
Chua Swee Kwang, Singapore, SG;
Low Siu Waf, Singapore, SG;
Chan Min Yu, Singapore, SG;
Neo Yong Loo, Singapore, SG;
Micron Technology, Inc., Boise, ID (US);
Abstract
A multichip assembly includes semiconductor devices or semiconductor device components with outer connectors on peripheral edges thereof. The outer connectors are formed by creating via holes along boundary lines between adjacent, unsevered semiconductor devices, or semiconductor device components, then plating or filling the holes with conductive material. When adjacent semiconductor devices or semiconductor device components are severed from one another, the conductive material in each via between the semiconductor devices is bisected. The semiconductor devices and components of the multichip assembly may have different sizes, as well as arrays of outer connectors with differing diameters and pitches. Either or both ends of each outer connector may be electrically connected to another aligned outer connector or contact area of another semiconductor device or component. Assembly in this manner provides a low-profile stacked assembly.