The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 17, 2007
Filed:
May. 05, 2005
Chi-hsuen Chang, Hsin-Chu, TW;
Jun Xiu Liu, Hsin-Chu, TW;
Tsung-yi Huang, Hsin-Chu, TW;
Chung-i Chen, Hsin-Chu, TW;
Tzu-chiang Sung, Jhubei, TW;
Chih Po Huang, Hsin-Chu, TW;
Rann Shyan Yeh, Hsin-Chu, TW;
Chi-Hsuen Chang, Hsin-Chu, TW;
Jun Xiu Liu, Hsin-Chu, TW;
Tsung-Yi Huang, Hsin-Chu, TW;
Chung-I Chen, Hsin-Chu, TW;
Tzu-Chiang Sung, Jhubei, TW;
Chih Po Huang, Hsin-Chu, TW;
Rann Shyan Yeh, Hsin-Chu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
Method and apparatus for a semiconductor device including high voltage MOS transistors is described. A substrate is provided with a low voltage and a high voltage region separated one from the other. Isolation regions containing an insulator are formed including at least one formed within one of said wells within the high voltage region. The angle of the transition from the active areas to the isolation regions in the high voltage device region is greater than a predetermined angle, in some embodiments it is greater than 40 degrees from vertical. In some embodiments the isolation regions are formed using shallow trench isolation techniques. In alternative embodiments the isolation regions are formed using field oxide formed by local oxidation of silicon techniques.