The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 16, 2007
Filed:
May. 06, 2003
Tazrien Kamal, San Jose, CA (US);
Yun Wu, Sunnyvale, CA (US);
Mark Ramsbey, Sunnyvale, CA (US);
Jean Yee-mei Yang, Sunnyvale, CA (US);
Arvind Halliyal, Cupertino, CA (US);
Rinji Sugino, San Jose, CA (US);
Hidehiko Shiraiwa, San Jose, CA (US);
Fred T K Cheung, San Jose, CA (US);
Tazrien Kamal, San Jose, CA (US);
Yun Wu, Sunnyvale, CA (US);
Mark Ramsbey, Sunnyvale, CA (US);
Jean Yee-Mei Yang, Sunnyvale, CA (US);
Arvind Halliyal, Cupertino, CA (US);
Rinji Sugino, San Jose, CA (US);
Hidehiko Shiraiwa, San Jose, CA (US);
Fred T K Cheung, San Jose, CA (US);
Spansion LLC, Sunnyvale, CA (US);
Abstract
The present invention, in one embodiment, relates to a process for fabricating a charge trapping dielectric flash memory device including steps of providing a semiconductor substrate having formed thereon a gate stack comprising a charge trapping dielectric charge storage layer and a control gate electrode overlying the charge trapping dielectric charge storage layer; forming an oxide layer over at least the gate stack; and depositing a spacer layer over the gate stack, wherein the depositing step deposits a spacer material having a reduced hydrogen content relative to a hydrogen content of a conventional spacer material.