The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 25, 2006
Filed:
Aug. 11, 1999
Akihisa Hongo, Tokyo, JP;
Naoaki Ogure, Tokyo, JP;
Hiroaki Inoue, Tokyo, JP;
Satoshi Sendai, Tokyo, JP;
Tetsuma Ikegami, Tokyo, JP;
Koji Mishima, Tokyo, JP;
Shuichi Okuyama, Tokyo, JP;
Mizuki Nagai, Tokyo, JP;
Ryoichi Kimizuka, Tokyo, JP;
Megumi Maruyama, Kanagawa, JP;
Akihisa Hongo, Tokyo, JP;
Naoaki Ogure, Tokyo, JP;
Hiroaki Inoue, Tokyo, JP;
Satoshi Sendai, Tokyo, JP;
Tetsuma Ikegami, Tokyo, JP;
Koji Mishima, Tokyo, JP;
Shuichi Okuyama, Tokyo, JP;
Mizuki Nagai, Tokyo, JP;
Ryoichi Kimizuka, Tokyo, JP;
Megumi Maruyama, Kanagawa, JP;
Ebara Corporation, Tokyo, JP;
Abstract
A method and apparatus plate a substrate to form wiring by efficiently filling a fine recess formed in a semiconductor substrate with plating metal without a void or contamination. The plating of the substrate to fill a wiring recess formed in the semiconductor substrate with plating metal includes performing an electroless plating process of forming an initial layer on the substrate, and performing an electrolytic plating process of filling the wiring recess with the plating metal, while the initial layer serves as a feeding layer.