The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 11, 2006
Filed:
Jun. 08, 2004
Applicants:
Jui-meng Jao, Miao-Li Hsien, TW;
Shing-ren Sheu, Tao-Yuan, TW;
Kuo-ming Chen, Hsin-Chu Hsien, TW;
Hung-min Liu, Hsin-Chu, TW;
Kun-chih Wang, Hsin-Chu, TW;
Inventors:
Jui-Meng Jao, Miao-Li Hsien, TW;
Shing-Ren Sheu, Tao-Yuan, TW;
Kuo-Ming Chen, Hsin-Chu Hsien, TW;
Hung-Min Liu, Hsin-Chu, TW;
Kun-Chih Wang, Hsin-Chu, TW;
Assignee:
United Microelectronics Corp., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
Abstract
A parasitic capacitance-preventing dummy solder bump structure on a substrate has at least one conductive layer formed on the substrate, a dielectric layer employed to cover the conductive layer, an under bump metallurgy layer (UBM layer) formed on the dielectric layer, and a solder bump formed on the UBM layer.