The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 14, 2006

Filed:

Feb. 24, 2004
Applicants:

Kuen-chyr Lee, Hsin-Chu, TW;

Liang-gi Yao, Hsin-Chu, TW;

Tien-chih Chang, Taipei, TW;

Chia-lin Chen, Hsinchu, TW;

Shih-chang Chen, Hsin-Chu, TW;

Mong-song Liang, Hsin-Chu, TW;

Inventors:

Kuen-Chyr Lee, Hsin-Chu, TW;

Liang-Gi Yao, Hsin-Chu, TW;

Tien-Chih Chang, Taipei, TW;

Chia-Lin Chen, Hsinchu, TW;

Shih-Chang Chen, Hsin-Chu, TW;

Mong-Song Liang, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/331 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for making an improved silicon-germanium layer on a substrate for the base of a heterojunction bipolar transistor is achieved using a two-temperature process. The method involves growing a seed layer at a higher temperature to reduce the grain size with shorter reaction times, and then growing an epitaxial Si—Ge layer with a Si cap layer at a lower temperature to form the intrinsic base with low boron out-diffusion. This results in an HBT having the desired narrow base profile while minimizing the discontinuities (voids) in the Si—Ge layer over the insulator to provide good electrical contacts and uniformity to the intrinsic base.


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