The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 07, 2006
Filed:
Sep. 18, 2003
Julie C. Biggs, Wappingers Falls, NY (US);
Tien-jen Cheng, Bedford, NY (US);
David E. Eichstadt, North Salem, NY (US);
Lisa A. Fanti, Hopewell Junction, NY (US);
Jonathan H. Griffith, Poughkeepsie, NY (US);
Randolph F. Knarr, Goldens Bridge, NY (US);
Sarah H. Knickerbocker, Hopewell Junction, NY (US);
Kevin S. Petrarca, Newburgh, NY (US);
Roger A. Quon, Beacon, NY (US);
Wolfgang Sauter, Richmond, VT (US);
Kamalesh K. Srivastava, Wappingers Falls, NY (US);
Richard P. Volant, New Fairfield, CT (US);
Julie C. Biggs, Wappingers Falls, NY (US);
Tien-Jen Cheng, Bedford, NY (US);
David E. Eichstadt, North Salem, NY (US);
Lisa A. Fanti, Hopewell Junction, NY (US);
Jonathan H. Griffith, Poughkeepsie, NY (US);
Randolph F. Knarr, Goldens Bridge, NY (US);
Sarah H. Knickerbocker, Hopewell Junction, NY (US);
Kevin S. Petrarca, Newburgh, NY (US);
Roger A. Quon, Beacon, NY (US);
Wolfgang Sauter, Richmond, VT (US);
Kamalesh K. Srivastava, Wappingers Falls, NY (US);
Richard P. Volant, New Fairfield, CT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method of forming wire bonds in (I/C) chips comprising: providing an I/C chip having a conductive pad for a wire bond with at least one layer of dielectric material overlying the pad; forming an opening through the dielectric material exposing a portion of said pad. Forming at least a first conductive layer on the exposed surface of the pad and on the surface of the opening. Forming a seed layer on the first conductive layer; applying a photoresist over the seed layer; exposing and developing the photoresist revealing the surface of the seed layer surrounding the opening; removing the exposed seed layer; removing the photoresist material in the opening revealing the seed layer. Plating at least one second layer of conductive material on the seed layer in the opening, and removing the first conductive layer on the dielectric layer around the opening. The invention also includes the resulting structure.