The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 18, 2005
Filed:
Dec. 29, 2003
Kuang-hsin Chen, Hsin-Chu, TW;
Hsun-chih Tsao, Hsin-Chu, TW;
Hung-wei Chen, Hsin-Chu, TW;
Di-hong Lee, Hsin-Chu, TW;
Chuan-ping Hou, Tainan, TW;
Jhi-cherng LU, Taipei, TW;
Kuang-Hsin Chen, Hsin-Chu, TW;
Hsun-Chih Tsao, Hsin-Chu, TW;
Hung-Wei Chen, Hsin-Chu, TW;
Di-Hong Lee, Hsin-Chu, TW;
Chuan-Ping Hou, Tainan, TW;
Jhi-Cherng Lu, Taipei, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
In a method of manufacturing a semiconductor device, an initial structure is provided. The initial structure includes a substrate, a patterned silicon layer, and a covering layer. The substrate has a buried insulator layer formed thereon. The patterned silicon layer is formed on the buried insulator layer. The covering layer is formed on the patterned silicon layer. A first layer is formed on the initial structure. Part of the first layer is removed with an etching process, such that a sidewall portion of the patterned silicon layer is exposed and such that a remaining portion of the first layer remains at a corner where the patterned silicon layer interfaces with the buried insulator layer. An oxide liner is formed on the exposed sidewall portion. A recess may be formed in the buried insulator layer (prior to forming the first layer) and may extend partially beneath the patterned silicon layer.