The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6952040 B1

PDF
Full Text
Expired
Date of Patent:
Oct. 04, 2005

Filed:

Jun. 29, 2001
Applicants:

Robert S. Chau, Beaverton, OR (US);

Jack Kavalieros, Portland, OR (US);

Anand Murthy, Portland, OR (US);

Brian Roberds, Beaverton, OR (US);

Brian S. Doyle, Portland, OR (US);

Inventors:

Robert S. Chau, Beaverton, OR (US);

Jack Kavalieros, Portland, OR (US);

Anand Murthy, Portland, OR (US);

Brian Roberds, Beaverton, OR (US);

Brian S. Doyle, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L029/76 ; H01L029/94 ; H01L031/062 ; H01L031/113 ;
U.S. Cl.
CPC ...
Abstract

A novel transistor structure and its method of fabrication. According to the present invention, the transistor includes an intrinsic silicon body having a first surface. A gate dielectric is formed on the first surface of the intrinsic silicon body. A gate electrode is formed on the gate dielectric wherein the gate electrode comprises a mid-gap work function film on the gate dielectric. A pair of source/drain regions are formed on opposite sides of the intrinsic silicon body.


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Chau, Robert. (2005). Transistor structure and method of fabrication (U.S. Patent No. 6952040). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6952040

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