The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 26, 2005
Filed:
Nov. 26, 2002
Susan H. Downey, Austin, TX (US);
Peter R. Harper, Round Rock, TX (US);
Kevin Hess, Austin, TX (US);
Michael V. Leoni, Austin, TX (US);
Tu-anh Tran, Austin, TX (US);
Susan H. Downey, Austin, TX (US);
Peter R. Harper, Round Rock, TX (US);
Kevin Hess, Austin, TX (US);
Michael V. Leoni, Austin, TX (US);
Tu-Anh Tran, Austin, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A bond pad () has a first wire bond region () and a second wire bond region (). In one embodiment, the first wire bond region () extends over a passivation layer (). In an alternate embodiment, a bond pad () has a probe region (), a first wire bond region (), and a second wire bond region (). In one embodiment, the probe region () and the wire bond region () extend over a passivation layer (). The bond pads may have any number of wire bond and probe regions and in any configuration. The ability for the bond pads to have multiple wire bond regions allows for multiple wire connections to a single bond pad, such as in multi-chip packages. The ability for the bond pads to extend over the passivation layer also allows for reduced integrated circuit die area.