The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 26, 2005
Filed:
Mar. 19, 2004
Min-lung Huang, Kaohsiung, TW;
Chi-long Tsai, Taitung, TW;
Chao-fu Weng, Tainan, TW;
Ching-huei Su, Kaohsiung, TW;
Min-Lung Huang, Kaohsiung, TW;
Chi-Long Tsai, Taitung, TW;
Chao-Fu Weng, Tainan, TW;
Ching-Huei Su, Kaohsiung, TW;
Advanced Semiconductor Engineering, Inc., Kaohsing, TW;
Abstract
A wafer bumping process is disclosed. A wafer having a plurality of bonding pads formed thereon is provided. A first under bump metallurgy layer is formed to cover the bonding pads. A first patterned photoresist layer having a plurality of first openings is formed on the first under bump metallurgy layer, wherein a portion of the first under bump metallurgy layer is exposed within the first openings. A second under bump metallurgy layer is formed within the first openings, wherein the second under bump metallurgy layer is much thicker than the first under bump metallurgy layer. A second patterned photoresist layer having a plurality of second openings is formed on the first patterned photoresist layer, wherein the second openings being larger than the first openings. After filling the second openings with a solder material, a reflowing process is performed to form a plurality of solder bumps, wherein the material of the second under bump metallurgy layer has a melting point higher than that of the solder material.