The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 12, 2005
Filed:
Aug. 27, 2002
Chun Chich Lin, Taichung, TW;
Yee-chia Yeo, Albany, CA (US);
Chien-chao Huang, Hsin-Chu, TW;
Chao-hsiung Wang, Hsinchu, TW;
Tien-chih Chang, Taipei, TW;
Chenming HU, Alamo, CA (US);
Fu-liang Yang, Hsin-Chu, TW;
Shih-chang Chen, Taoyuan, TW;
Mong-song Liang, Hsin-Chu, TW;
Liang-gi Yao, Hsinchu, TW;
Chun Chich Lin, Taichung, TW;
Yee-Chia Yeo, Albany, CA (US);
Chien-Chao Huang, Hsin-Chu, TW;
Chao-Hsiung Wang, Hsinchu, TW;
Tien-Chih Chang, Taipei, TW;
Chenming Hu, Alamo, CA (US);
Fu-Liang Yang, Hsin-Chu, TW;
Shih-Chang Chen, Taoyuan, TW;
Mong-Song Liang, Hsin-Chu, TW;
Liang-Gi Yao, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
A method of forming a strained silicon layer on a relaxed, low defect density semiconductor alloy layer such as SiGe, has been developed. In a first embodiment of this invention the relaxed, low density SiGe layer is epitaxially grown on an silicon layer which in turn is located on an underlying SiGe layer. During the epitaxial growth of the overlying SiGe layer defects are formed in the underlying silicon layer resulting in the desired, relaxation, and decreased defect density for the SiGe layer. A second embodiment features an anneal procedure performed during growth of the relaxed SiGe layer, resulting in additional relaxation and decreased defect density, while a third embodiment features an anneal procedure performed to the underlying silicon layer prior to epitaxial growth of the relaxed SiGe layer, again allowing optimized relaxation and defect density to be realized for the SiGe layer. The ability to obtain a strained silicon layer on a relaxed, low defect density SiGe layer, allows devices with enhanced carrier mobility to be formed in the surface of the strained silicon layer, with decreased risk of leakage due the presence of the underlying, relaxed, low defect density SiGe layer.