The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 18, 2005
Filed:
Mar. 12, 2003
Karen Maex, Herent, BE;
Ricardo A. Donaton, Cortlandt Manor, NY (US);
Michael Baklanov, Leuven, BE;
Serge Vanhaelemeersch, Leuven, BE;
Herbert Struyf, Kontich, BE;
Marc Schaekers, Leuven, BE;
Karen Maex, Herent, BE;
Ricardo A. Donaton, Cortlandt Manor, NY (US);
Michael Baklanov, Leuven, BE;
Serge Vanhaelemeersch, Leuven, BE;
Herbert Struyf, Kontich, BE;
Marc Schaekers, Leuven, BE;
Interuniversitair Microelektronica Centrum, Leuven, BE;
Abstract
A method for anisotropic plasma etching of organic-containing insulating layers is disclosed. According to this method at least one opening is created in an organic-containing insulating layer formed on a substrate. These openings are created substantially without depositing etch residues by plasma etching said insulating layer in a reaction chamber containing a gaseous mixture which is composed such that the plasma etching is highly anisotropic. Examples of such gaseous mixtures are a gaseous mixture comprising a fluorine-containing gas and an inert gas, or a gaseous mixture comprising an oxygen-containing gas and an inert gas, or a gaseous mixture comprising HBr and an additive. The plasma etching of the organic-containing insulating layer can be performed using a patterned bilayer as an etch mask, said bilayer comprising a hard mask layer, being formed on said organic-containing insulating layer, and a resist layer being formed on said hard mask layer. A method is disclosed for forming a layer, protecting exposed surfaces of low-k dielectrics. More particularly the method comprises the steps of sealing exposed surfaces of a, preferably porous, low-k dielectric, by forming a protective layer on exposed surfaces during or after the step of patterning openings in the porous dielectric layers. Preferably this protective layer is formed by a N2/O2 plasma treatment of the exposed surfaces.