The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 02, 2003
Filed:
Jan. 12, 2001
Stephen D. Coomer, Tempe, AZ (US);
John Francis McIntee, Gold Canyon, AZ (US);
Jozsef Michael Iha, Gold Canyon, AZ (US);
Robert T. Borra, Austin, TX (US);
Eric Lusby, Mesa, AZ (US);
Michael J. Lombardi, Phoenix, AZ (US);
Tokyo Electron Limited, Tokyo, JP;
Abstract
Apparatus and methods for a wafer handling system that manipulates semiconductor wafers. The present invention includes an end effector having a vacuum chuck, an internal vacuum plenum, and a plurality of flow diverters positioned within the vacuum plenum to define vacuum distribution channels in fluid communication with respective vacuum ports of the vacuum chuck. The present invention also includes a vacuum chuck having flow diverters positioned in one or more internal vacuum plenums which are in fluid communication with the vacuum ports of the vacuum chuck. The flow diverters of the vacuum chucks adjust the vacuum pressure supplied to the vacuum ports such that, as vacuum ports are occluded by the wafer, the vacuum pressure is preferentially applied to unblocked vacuum ports for increasing the attractive force applied to unengaged portions of the wafer. The wafer handling system also includes a gas dispensing showerhead that may be positioned above a vacuum chuck for flattening the wafer so that a vacuum chuck can establish a secure engagement. The apparatus of the present invention has particularly utility for securing thin semiconductor wafers with a significant warpage.