The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 24, 2002
Filed:
Nov. 01, 2000
Ling Chen, Sunnyvale, CA (US);
Seshadri Ganguli, Sunnyvale, CA (US);
Wei Cao, Milpitas, CA (US);
Christophe Marcadal, Santa Clara, CA (US);
Applied Materials, Inc., Santa Clara, CA (US);
Abstract
A method and resultant structure of forming barrier layers in a via hole extending through an inter-level dielectric layer. A first barrier layer of TiSiN is conformally coated by chemical vapor deposition onto the bottom and sidewalls of the via holes and in the field area on top of the dielectric layer. A single plasma sputter reactor is used to perform two steps. In the first step, the wafer rather than the target is sputtered with high energy ions to remove the barrier layer from the bottom of the via but not from the sidewalls. In the second step, a second barrier layer, for example of Ta/TaN, is sputter deposited onto the via bottom and sidewalls. The two steps may be differentiated by power applied to the target, by chamber pressure, or by wafer bias. The second step may include the simultaneous removal of the first barrier layer from the via bottom and sputter deposition of the second barrier layer onto the via sidewalls. Chamber conditions in the first step, including balancing neutrals and ions, may be controlled to remove the first barrier layer from the via bottom while leaving it on the more exposed the field area.