The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 11, 2005
Filed:
Oct. 25, 2003
Ling Chen, Sunnyvale, CA (US);
Seshadri Ganguli, Sunnyvale, CA (US);
Wei Cao, Milpitas, CA (US);
Christophe Marcadal, Santa Clara, CA (US);
Ling Chen, Sunnyvale, CA (US);
Seshadri Ganguli, Sunnyvale, CA (US);
Wei Cao, Milpitas, CA (US);
Christophe Marcadal, Santa Clara, CA (US);
Applied Materials, Inc., Santa Clara, CA (US);
Abstract
A method of forming barrier layers in a via hole extending through an inter-level dielectric layer and including a preformed first barrier coated onto the bottom and sidewalls of the via holes. In a single plasma sputter reactor, a first step sputters the wafer rather than the target with high energy ions to remove the barrier layer from the bottom of the via but not from the sidewalls and a second step sputter deposits a second barrier layer, for example of Ta/TaN, onto the via bottom and sidewalls. The two steps may be differentiated by power applied to the target, by chamber pressure, or by wafer bias. The second step may include the simultaneous removal of the first barrier layer from the via bottom and sputter deposition of the second barrier layer onto the via sidewalls.