The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 17, 2002

Filed:

Mar. 17, 2000
Applicant:
Inventors:

John J. Ellis-Monaghan, Grand Isle, VT (US);

Paul M. Feeney, Aurora, IL (US);

Robert M. Geffken, Burlington, VT (US);

Howard S. Landis, Underhill, VT (US);

Rosemary A. Previti-Kelly, Burlington, VT (US);

Bette L. Bergman Reuter, Essex Junction, VT (US);

Matthew J. Rutten, Milton, VT (US);

Anthony K. Stamper, Williston, VT (US);

Sally J. Yankee, Underhill, VT (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/358 ;
U.S. Cl.
CPC ...
H01L 2/358 ;
Abstract

A method and structure for a semiconductor chip includes a plurality of layers of interconnect metallurgy, at least one layer of deformable dielectric material over the interconnect metallurgy, at least one input/output bonding pad, and a support structure that includes a substantially rigid dielectric in a supporting relationship to the pad that avoids crushing the deformable dielectric material.


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