The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 04, 2002
Filed:
Mar. 20, 2000
Jaime Bayan, Palo Alto, CA (US);
Peter Howard Spalding, Cupertino, CA (US);
Harry Cheng Hong Kam, Melaka, MY;
Ah Lek Hu, Melaka, MY;
Sharon Mei Wan Ko, Melaka, MY;
Santhiran Nadarajah, Malacca, MY;
Aik Seng Kang, Melaka, MY;
Yin Yen Bong, Melaka, MY;
National Semiconductor Corporation, Santa Clara, CA (US);
Abstract
A variety of techniques for electrically debussing conductive substrate panels used in the formation of a matrix of leadless integrated circuit packages are described. Generally, after a matrix of leadless packages have been fabricated in panel form on a conductive substrate panel, tie bars that are used to support contacts and potentially other structures on the conductive substrate are removed after plastic caps have been molded over the matrix, but before separating the packaged devices. This serves to electrically isolate the contacts from one another while leaving sufficient portions of the molded substrate structure in tact to facilitate handling the structure in panel form. With the described arrangement, the packaged devices may be tested in panel form. After testing and any other desired panel based operations, the packaged devices may be separated using conventional techniques. The removal of the tie bars can be accomplished by any suitable technique including, for example, sawing or etching.