The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 02, 2002
Filed:
Jan. 19, 2000
Naoki Fukutomi, Yuki, JP;
Yoshiaki Tsubomatsu, Tsuchiura, JP;
Fumio Inoue, Tsukuba, JP;
Toshio Yamazaki, Tsukuba, JP;
Hirohito Ohhata, Tsukuba, JP;
Shinsuke Hagiwara, Shimodate, JP;
Noriyuki Taguchi, Tsukuba, JP;
Hiroshi Nomura, Oyama, JP;
Abstract
A semiconductor package substrate is provided, which can meet the move toward high integration of semiconductors. A nickel layer is plated on an electroplated copper foil to form a wiring pattern. An LSI chip is mounted on the copper foil, and terminals of the LSI chip and the wiring pattern are connected by wire bonding, followed by sealing with a semiconductor-sealing epoxy resin. Only the copper foil is dissolved away with an alkali etchant to expose nickel. With a nickel stripper having low copper-dissolving power, the nickel layer is removed to expose the wiring pattern. A solder resist is coated, and a pattern is formed in such a way that connecting terminal portions are exposed. Solder balls are placed at the exposed portions of the wiring pattern and are then fused. The wiring pattern is connected to an external printed board via the solder balls.