The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 14, 2001
Filed:
Aug. 11, 2000
Wan Le Xie, Taipei, TW;
Fu Yu Huang, Taipei, TW;
Yung-Cheng Chuang, Taipei, TW;
Ning Huang, Taipei, TW;
Chung Ming Chang, Taipei, TW;
Hui-Pin Chen, Taipei, TW;
Chia-Chieh Hu, Taipei, TW;
Feng Chang Tu, Taipei, TW;
Hsuan Jui Chang, Taipei, TW;
Hua Wen Chiang, Taipei, TW;
Orient Semiconductor Electronics Limited, Kaohsiung, TW;
Abstract
A process of manufacturing thin ball array substrates includes the steps of: using a layer of polyimide film as a carrier, electroplating a thin copper layer on the polyimide film, electroplating a thick copper layer on the thin copper layer, applying photosensitive coating layers on both sides of the carrier, mounting two masks with optically transmissible circuit tracks on two sides of the carrier and then processing the carrier with exposure treatment, processing the carrier with development treatment so as to remove the photosensitive coating layers aligned with the circuit track thereby forming recessed circuit tracks on the photosensitive coating layers, electroplating a copper layer on a top of the carrier thereby forming an additional copper layer on the thick copper layer, etching a bottom of the carrier to remove the upper recessed circuit track thereon, coating the copper layer on the upper recessed circuit track with soldering metallic material so as to make a top of the soldering metallic material, washing away the photosensitive coating layers with chemical agent, and removing surplus copper layer to remain in circuit lines and the soldering metallic material, whereby a thin ball grid array substrate with thicker circuit lines without remaining electroplating lines can be obtained.