The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 20, 2000
Filed:
Aug. 28, 1996
Yuji Ezaki, Tsuchiura, JP;
Shinya Nishio, Musashimurayama, JP;
Fumiaki Saitoh, Akishima, JP;
Hideo Nagasawa, Ohme, JP;
Toshiyuki Kaeriyama, Yawara-mura, JP;
Songsu Cho, Fujishiro-machi, JP;
Hisao Asakura, Ohme, JP;
Jun Murata, Kunitachi, JP;
Yoshitaka Tadaki, Hannoh, JP;
Toshihiro Sekiguchi, Hidaka, JP;
Keizo Kawakita, Ohme, JP;
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A method of making semiconductor devices which enables control of the impurity concentration and fine patterning by making removal of residual stress due LOCOS oxidation compatible with the formation of deep wells. A selective oxide layer is formed for separating element regions on a principal plane of a semiconductor substrate, for example, a p.sup.- -type silicon substrate 1. A mask is formed (for example photoresist 47) on the surface including the selective oxide layer and impurities (for example phosphorous) of a conductivity type opposite that of the semiconductor substrate are introduced via an opening in the mask. Then the selective oxide film is annealed by a high-temperature treatment while a deep well (for example n-type deep well 50) is formed by introducing the impurities.