The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 16, 1999
Filed:
Apr. 30, 1997
David L Edwards, Poughkeepsie, NY (US);
Armando S Cammarano, Hyde Park, NY (US);
Jeffrey T Coffin, Pleasant Valley, NY (US);
Mark G Courtney, Poughkeepsie, NY (US);
Stephen S Drofitz, Jr, Wappingers Falls, NY (US);
Michael J Ellsworth, Jr, Poughkeepsie, NY (US);
Lewis S Goldmann, Bedford, NY (US);
Sushumna Iruvanti, Wappingers Falls, NY (US);
Frank L Pompeo, Montgomery, NY (US);
William E Sablinski, Beacon, NY (US);
Raed A Sherif, Croton, NY (US);
Hilton T Toy, Wappingers Falls, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
The present invention relates generally to a new scheme of providing a seal band for semi-conductor substrates and chip carriers. More particularly, the invention encompasses a structure and a method that uses a multi-layer metallic seal to provide protection to chips on a chip carrier. This multi-layer metal seal provides both enhanced hermeticity lifetime and environmental protection. For the preferred embodiment the multi-layer metallic seal band is a three layer, solder sandwich structure which is used to create a low cost, high reliability, hermetic seal for the module. This solder sandwich has a high melting temperature thick solder inner core, and lower melting point thin interconnecting solder layers, where the thin interconnecting solder layers may have similar or different melting points.