The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 16, 1997
Filed:
Dec. 02, 1994
Takashi Yoshitomi, Yokohama, JP;
Masanobu Saito, Chiba, JP;
Hisayo Momose, Tokyo-to, JP;
Hiroshi Iwai, Kawasaki, JP;
Yukihiro Ushiku, Yokohama, JP;
Mizuki Ono, Yokohama, JP;
Yasushi Akasaka, Yokohama, JP;
Hideaki Nii, Yokohama, JP;
Satoshi Matsuda, Yokohama, JP;
Yasuhiro Katsumata, Chigasaki, JP;
Tatsuya Ooguro, Yokohama, JP;
Claudio Fiegna, Bologna, IT;
Kabushiki Kaisha Toshiba, Kawasaki, JP;
Abstract
A MOS type semiconductor device has a gate whose length is 170 nm (0.17 .mu.m) or less, a junction depth of source and drain diffusion layers in the vicinity of a channel is 22 nm or less, and a concentration of impurities at the surface in the source and drain diffusion layers is made to 10.sup.20 cm.sup.-3 or more. Such structure is obtained using solid phase diffusion using heat range from 950.degree. C. to 1050.degree. C. and/or narrowing gate width by ashing or etching. The other MOS type semiconductor device is characterized in that the relationship between the junction depth x.sub.j �nm! in the source and drain diffusion layer regions and the effective channel length L.sub.eff �nm! is determined by L.sub.eff >0.69 x.sub.j -6.17.