The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 22, 1991

Filed:

Nov. 01, 1988
Applicant:
Inventors:

Michio Takahashi, Yokohama, JP;

Tooru Mita, Yokohama, JP;

Yasuo Nakagawa, Chigasaki, JP;

Toshimitsu Hamada, Yokohama, JP;

Hisafumi Iwata, Yokohama, JP;

Aizo Kaneda, Yokohama, JP;

Kouji Serizawa, Fujisawa, JP;

Hiroyuki Tanaka, Yokohama, JP;

Koichi Sugimoto, Hiratsuka, JP;

Toshihiko Sakai, Yokohama, JP;

Keizo Matsukawa, Kokubunji, JP;

Tsutomu Mimata, Akikawa, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437220 ; 364477 ; 219 561 ; 219 8518 ;
Abstract

The present invention relates to a multi-pin chip mounting method and apparatus based on a TAB (Tape Automated Bonding) system in which leads formed on a tape and bumps formed an IC chip are aligned with each other and compress-bonded to each other. An IC chip having bumps formed on a surface thereof and inner leads formed on a carrier tape are disposed opposite to each other at a bonding station. A position of the IC chip on a stage is detected through the inner leads at the bonding station to determine the amount of correction of position of the stage. The inner leads and the IC chip are aligned with each other on the basis of the determined correction amount and are thereafter bonded to each other.


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