The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2026

Filed:

Oct. 01, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Scott B. Clendenning, Portland, OR (US);

Sudarat Lee, Hillsboro, OR (US);

Kevin P. O'brien, Portland, OR (US);

Rachel A. Steinhardt, Beaverton, OR (US);

John J. Plombon, Portland, OR (US);

Arnab Sen Gupta, Hillsboro, OR (US);

Charles C. Mokhtarzadeh, Portland, OR (US);

Gauri Auluck, Hillsboro, OR (US);

Tristan A. Tronic, Aloha, OR (US);

Brandon Holybee, Portland, OR (US);

Matthew V. Metz, Portland, OR (US);

Dmitri Evgenievich Nikonov, Beaverton, OR (US);

Ian Alexander Young, Olympia, WA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/47 (2025.01); H10D 30/01 (2025.01); H10D 30/69 (2025.01); H10D 62/10 (2025.01); H10P 14/692 (2026.01);
U.S. Cl.
CPC ...
H10D 30/47 (2025.01); H10D 30/024 (2025.01); H10D 30/701 (2025.01); H10D 62/118 (2025.01); H10P 14/69398 (2026.01);
Abstract

Technologies for a field effect transistor (FET) with a ferroelectric gate dielectric are disclosed. In an illustrative embodiment, a perovskite stack is grown on a buffer layer as part of manufacturing a transistor. The perovskite stack includes one or more doped semiconductor layers alternating with other lattice-matched layers. Growing the doped semiconductor layers on lattice-matched layers can improve the quality of the doped semiconductor layers. The lattice-matched layers can be etched away, leaving the doped semiconductor layers as fins for a ribbon FET. A ferroelectric layer can be conformally grown on the fins, creating a high-quality ferroelectric layer above and below the fins. A gate can then be grown on the ferroelectric layer.


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Clendenning, Scott. (2026). Technologies for atomic layer deposition for ferroelectric transistors (U.S. Patent No. 12787339). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12787339

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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