The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 20, 2026

Filed:

May. 04, 2023
Applicant:

Xintec Inc., Taiwan, TW;

Inventors:

PO-Han Lee, Taipei City, TW;

Tsang Yu Liu, Zhubei City, TW;

Chia-Ming Cheng, New Taipei City, TW;

Kuei Wei Chen, Taoyuan City, TW;

Jiun-Yen Lai, Taoyuan City, TW;

Assignee:

Xintec Inc., Taoyuan City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10F 39/00 (2025.01); H10W 72/00 (2026.01); H10W 72/30 (2026.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10F 39/804 (2025.01); H10F 39/026 (2025.01); H10W 72/0198 (2026.01); H10W 72/07353 (2026.01); H10W 72/07354 (2026.01); H10W 72/07554 (2026.01); H10W 72/331 (2026.01); H10W 72/337 (2026.01); H10W 72/347 (2026.01); H10W 72/354 (2026.01); H10W 72/865 (2026.01); H10W 72/884 (2026.01); H10W 90/734 (2026.01); H10W 90/754 (2026.01);
Abstract

A chip package includes a carrier board, a chip, a light transmissive sheet, a supporting element, and a molding material. The chip is located on the carrier board and has a sensing area. The light transmissive sheet is located above the supporting element and covers the sensing area of the chip. The supporting element is located between the light transmissive sheet and the chip, and surrounds the sensing area of the chip. The molding material is located on the carrier board and surrounds the chip and the light transmissive sheet. A top surface of the molding material is lower than a top surface of the light transmissive sheet.


Find Patent Forward Citations

Lee, PO-Han. (2026). Chip package and manufacturing method thereof (U.S. Patent No. 12772583). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12772583

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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