The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 20, 2026
Filed:
Jun. 27, 2022
Intel Corporation, Santa Clara, CA (US);
Carl H. Naylor, Portland, OR (US);
Kirby Maxey, Hillsboro, OR (US);
Kevin P. O'brien, Portland, OR (US);
Chelsey Dorow, Portland, OR (US);
Sudarat Lee, Hillsboro, OR (US);
Ashish Verma Penumatcha, Beaverton, OR (US);
Uygar E. Avci, Portland, OR (US);
Matthew V. Metz, Portland, OR (US);
Scott B. Clendenning, Portland, OR (US);
Jiun-Ruey Chen, Hillsboro, OR (US);
Chia-Ching Lin, Portland, OR (US);
Carly Rogan, North Plains, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Embodiments described herein may be related to apparatuses, processes, and techniques directed to creating a transistor structure by selectively growing a 2D TMD directly in a stacked channel configuration, such as a stacked nanowire or nanoribbon formation. In embodiments, this TMD growth may occur for all of the nanowires or nanoribbons in the transistor structure in one stage. Placement of a SAM on a plurality of dielectric layers within the transistor structure stack facilitates channel deposition and channel geometry in the stacked channel configuration. Other embodiments may be described and/or claimed.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile