The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 22, 2026
Filed:
Jun. 29, 2022
Intel Corporation, Santa Clara, CA (US);
Sagar Suthram, Portland, OR (US);
Debendra Mallik, Chandler, AZ (US);
John Heck, Berkeley, CA (US);
Pushkar Sharad Ranade, San Jose, CA (US);
Ravindranath Vithal Mahajan, Chandler, AZ (US);
Thomas Liljeberg, San Jose, CA (US);
Wilfred Gomes, Portland, OR (US);
Abhishek A. Sharma, Hillsboro, OR (US);
Tahir Ghani, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Embodiments of a microelectronic assembly comprise: a plurality of microelectronic sub-assemblies arranged in an array; and a plurality of photonic integrated circuit (PIC) dies, each PIC die having waveguides. Adjacent microelectronic sub-assemblies are coupled to one of the PIC dies by interconnects such that any one PIC die is coupled to more than two adjacent microelectronic sub-assemblies, and the microelectronic sub-assemblies coupled to each PIC die in the plurality of PIC dies are communicatively coupled by the waveguides in the PIC die. Each microelectronic sub-assembly comprises: an interposer integrated circuit (IC) die comprising one or more electrical controller circuit proximate to at least one edge of the interposer IC die; a first plurality of IC dies coupled to a first surface of the interposer IC die; and a second plurality of IC dies coupled to an opposing second surface of the interposer IC die.